Based on recent issue fixes and functional improvements, the FPGA version for the A/B series modules 

has been uniformly updated to 6212.

The main improvements for the A series are:

1. Fixed the issue where the IIS clock switches during initialization when using non-TDM2 formats.

2. Added mix output delay and master/standby function settings. The default mode is master/standby.

   If users want to use the mix delay output function, they should set bit 15 of register 6 to 1.

3. Added a self-configuration option in the configuration file to enable/disable modules.

The B series mainly improves the clock algorithm based on version 6207 to enhance clock accuracy.